The present invention relates in general to circuit design and, more particularly, to interactive computer-aided design where clock-based scheduling of high-level design language statements are graphically displayed for easy manipulation.
Techniques of computer-aided design are well known and practiced in digital and analog circuit design. A typical process involves identifying a circuit design task and specifying a high-level functional description of the overall circuit function. That functional description may either be manually implemented in a specific circuit design or fed into computer-aided design software that automatically configures the circuit implementation. Additional computer-aided design software takes the computer generated implementation and creates gate-level schematics, layouts, and masks that are sent to a fabrication facility to build the integrated circuit.
The computer-aided design software creates the circuit implementation from a set of rigid design rules whereby a functional description is transformed into a circuit implementation under a predetermined style, i.e. configuration of busses, multiplexers, interconnects and registers and selection of functional units. For example, if the high-level functional description includes an addition operation in one area and a subtraction operation in another area, a conventional computer-aided design software may pull an adder from its library and implement it in the circuit schematic and then pull a subtractor from its library and implement it in another area of the circuit schematic to perform each operation. In some applications having a large number of such addition and subtraction operations it is preferable to share adders and subtractors for addition and subtraction operations, or use a more complex general purpose arithmetic logic unit instead of using numerous dedicated adders and subtractors. Unfortunately, the designer typically does not have control over whether the computer-aided design software selects the general purpose arithmetic logic unit or a plurality of individual arithmetic components. In the prior art the designer has often been forced to accept whatever circuit implementation is dictated by the logic of the computer-aided design software. Since the architectural design of many circuits is as much an art as a science it is desirable to allow the designer more control and flexibility over the actual implementation of the circuit from the high-level descriptive language.
The computer-aided design software known in the prior art generally involves a mapping step where the functional description is transformed into a structural layout. A scheduling process must also be defined to determine which functional steps are performed in which order. For example, in a synchronous digital design it may be necessary to perform certain mathematical calculations to determine intermediate results before the next mathematical calculations that use those results are performed. A scheduling control circuit provides the appropriate enable signals and clock signals to the circuit schematic to perform the mathematical calculations in the correct order to achieve the desired result. For applications that require very precise control over the scheduling of the circuit operations, it is often necessary for the designer to put detailed timing and control instructions within the functional description to ensure that the operations are performed in the correct order. Otherwise, the computer-aided design software may produce inappropriate ordering that may produce undesired results and occasionally the implementation may actually be incorrect. The scheduling control in the functional description may become impractical or at least cumbersome for complex loops, conditional statements and pipe-lining.
Hence, a need exists for a method of allowing interaction between the designer and computer-aided design software so that the designer may exercise control over particular implementations of a functional description.